1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a self-aligned etching process.
2. Description of the Related Art
When the deep sub-micron process is used in semiconductor manufacturing, the size of a device becomes smaller so that the operating speed of the integrated circuit is efficiently enhanced. Regarding semiconductor devices with the same circuit pattern, the operating speed of the circuit depends on the density of interior devices. In the case of the high density of devices, such as a DRAM (Dynamic Random Access Memory), the space between a bit line and a node contact of a capacitor must decrease, and thus the insulation between them becomes a hard-to-solve problem.
One solution is to form a self-aligned contact. A cap and spacers, both made of silicon nitride, are formed on the top and sidewalls of a bit line, and then a silicon oxide layer is formed thereon. Second, due to different chemical properties of silicon nitride and silicon oxide, by selectively etching silicon oxide, the silicon oxide layer is etched in a self-aligned fashion to form a node contact opening between adjacent bit lines. The bit line is protected during etching because of the silicon nitride cap and spacers, which therefore maintain a good insulation between the bit line and the node contact.
However, in the above case, the dielectric constant of silicon nitride is relatively high, about 7 to 8; thus, a higher bit line capacitance arises (because a capacitor comprising the node contact, a dielectric layer and the bit line in sequence is formed) and a severe coupling effect between adjacent bit lines is induced. This situation seriously affects the accuracy of data reading. For example, in the case of a 64 Mbits DRAM, the general selection principal for using a material or a combination of materials as an insulator between adjacent bit lines is that the induced equivalent bit line capacitance of a section having a capacity of 512 bits must be less than 120 fF; i.e., the equivalent bit line capacitance of each bit must be less than 0.23 fF, which can thereby prevent the data address in a memory from being misjudged.
In addition, greater thermal stress exists between silicon nitride and silicon, and exists between silicon nitride and tungsten silicide as well, which increases the difficulty with which the process is controlled.
Therefore, a need exists for a method of forming a node contact in a self-aligned fashion to prevent the above problems.